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Low voltage cascode amplifier

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journal contribution
posted on 21.05.2021, 15:52 by Shahab Ardalan, Kaamran Raahemifar, Fei Yuan
A 0.8 V folded cascode operational amplifier was designed in 0.18 /spl mu/m standard CMOS technology. Emphasis was placed on observing the low voltage design and using a current driven bulk (CDB) technique to achieve this goal. The CDB technique was introduced as a method for low voltage design by reducing the threshold voltage. This design achieves 141 dB DC gain, 56 MHz 3 dB bandwidth and 65 GHz gain bandwidth, which is the working condition of pipeline ADCs.

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Editor

Ryerson University

Language

eng