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A 100 MHz - 1 GHz on-chip-programmable phase-locked-loop

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thesis
posted on 22.05.2021, 10:18 by Haleh Vahedi Vahedi
A programmable wide-range PLL has been designed that can provide 100-MHz to 1-GHz rail-to-rail digital clock signal from a 50-MHz reference clock. The architecture is appropriate for low-power design and is also power-efficient. The system is robust against temperature changes so that the stability of the system is guaranteed. Because of the differential configuration of the sub-blocks and using a voltage-controlled oscillator with a 1Ow. gain and a linear transfer function the system has an acceptable noise rejection.

History

Language

eng

Degree

Master of Applied Science

Program

Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type

Thesis