Li, Yue.pdf (11.62 MB)
Download file

Adaptive Data-Transition Decision Feedback Equalizers For High-Speed Serial Links

Download (11.62 MB)
thesis
posted on 21.12.2021, 14:26 by Yue Li
This dissertation investigates adaptive decision feedback equalizers for high-speed serial data links.
An adaptive data-transition decision feedback equalizer (DT-DFE) was developed. The DT-DFE boosts the eye-opening of the high-frequency components of data without attenuating their low-frequency counterparts. Reference voltages were obtained by transmitting consecutive 1s and 0s and measuring the output of the continuous-time linear equalizer using a pair of successive approximation register analog-to-digital converters in a training phase. It uses loop unrolling to detect data transitions, activate tap-tuning, launch DFE, and combat timing constraints. The performance of the DT-DFE and its advantages over commonly used data-state DFE were validated using the schematic-level simulation results of 5 Gbps backplane links.
A new adaptive DT-DFE with edge-emphasis (EE) taps and raised references was developed. Loop-unrolling was further developed for DT-DFE with EE-taps. The reference voltages were raised beyond that set by the low-frequency components of data to increase vertical eye-opening. Clock and data recovery was performed using 4x oversampling. The DT-DFE was validated using the schematiclevel simulation results of 10 Gbps backplane links.
A pre-skewed bi-directional gated delay line (BDGDL) bang-bang frequency difference-to-digital converter and a BDGDL integrating frequency difference-todigital converter (iFDDC) were proposed for clock and data recovery. Both frequency difference detectors feature all-digital realization, low power consumption, and high-speed operation. The built-in integration of iFDDC results in a zero static frequency error and the first-order noise-shaping of the quantization errors of the BDGDL and digitally-controlled oscillators. Their effectiveness was validated using schematic-level simulation results of 5-GHz frequency-locked loops.
All systems validating the proposed adaptive DFE and frequency-difference detectors were designed in TSMC’s 65 nm CMOS technology and analyzed using Spectre from Cadence Design Systems.

History

Language

English

Degree

Doctor of Philosophy

Program

Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type

Dissertation

Thesis Advisor

Fei Yuan