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CMOS Digital Pixel Sensors With In-Pixel Analog-To-Digital Conversion

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posted on 23.05.2021, 12:33 by Yong Chen
This thesis deals with the designing of CMOS image sensors with in-pixel analog-to-digital conversion. A 2-stage memory write scheme for Pulse-Width-Modulation digital pixel sensors is proposed. It utilizes the characteristics of Gray-code counters and partitions a single data write operation into two separated write operations such that the size of the in-pixel memory can be significantly reduced. A Pulse-Frequency-Modulation pixel significantly reduces the integration time without sacrificing the dynamic range. Finally, a Pulse-Frequency-Modulation Digital Pixel Sensor with an in-pixel variable reference voltage is proposed. As compared with conventional Pulse-Frequency-Modulation pixels, the proposed architecture improves the dynamic range by adaptively adjusting the reference voltage in the pixel. All proposed digital pixel sensors are designed in TSMC-0.18μm 6-Metal 1-Poly 1.8 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. The effectiveness of the proposed digital pixel sensors is validated using simultation.





Master of Applied Science


Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type


Thesis Advisor

Fei Yuan Gul N. Khan