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On-chip interconnects modeling and timing driven buffer insertion

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posted on 22.05.2021, 11:31 by Alaa R. Abdullah
With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.





Master of Applied Science


Electrical and Computer Engineering

Granting Institution

Ryerson University Ryerson University

LAC Thesis Type


Thesis Advisor

Adnan Kabbani