Qendri_Dhimiter.pdf (2.03 MB)

REAL TIME VIDEO STITCHING IMPLEMENTATION ON A ZYNQ FPGA SOC

Download (2.03 MB)
thesis
posted on 23.05.2021, 13:27 by Dhimiter Qendri
This project details the design and implementation of an image processing pipeline that targets real time video-stitching for semi-panoramic video synthesis. The scope of the project includes the analysis of possible approaches, selection of processing algorithms and procedures, design of experimental hardware set-up (including the schematic capture design of a custom catadioptric panoramic imaging system) and firmware/software development of the vision processing system components. The goal of the project is to develop a frame-stitching IP module as well as an efficient video registration algorithm capable for synthesis of a semi-panoramic video-stream at 30 frames-per-second (fps) rate with minimal FPGA resource utilization. The developed components have been validated in hardware. Finally, a number of hybrid architectures that make use of the synergy between the CPU and FPGA section of the ZYNQ SoC have been investigated and prototyped as alternatives to a complete hardware solution. Keyword: Video stitching, Panoramic vision, FPGA, SoC, vision system, registration

History

Language

eng

Degree

Master of Engineering

Program

Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type

Thesis

Usage metrics

Electrical and Computer Engineering (Theses)

Keywords

Exports