Switch-level dynamic fault modeling for resistive short and open faults in nanometre technologies
thesisposted on 23.05.2021, 15:02 authored by Mayuri Kunchwar
Modeling the dynamic behaviour of resistive shorts and opens at switch-level dictates the characterization o enhanced delay attributable to these faults with referenc to the input combinations, fault sites, defect resistance and CMOS technology variation. Resistive physical failures make the output voltage fluctuate between intermediate ranges by disturbing the propagation time of the logic, without adversely changing the functional output. To determine the impact of logic propagation delay (tp) on the output voltage (Vout) of a gate, a switch-level fault analysis on CMOS primitive gates is executed for CMOS technologies 350 nm, 180 nm, and 90 nm in comparison with nanometre technologies 45 nm and 32 nm. To understand the nature and effect of actual resistive faults in silicon, static faults in static primitive gates are reviewed after altering the defect resistance. Delay and output voltage changes induced by these variations are determined for CMOS 32 nm technology.