Utilization of differential pulse position modulation in designing time-mode serial data links
thesisposted on 08.06.2021, 11:04 by Taha Mehrabi Shahsavari
A new differential time-based architecture for use in serial communication data links is presented in this thesis, the main idea of which involves transmitting the difference between the input clock signal and the data signal to the receiver. A time to digital converter (TDC) is then used to demodulate the data from the differential pulse position modulated signal. The proposed design substantiates an improvement in the bandwidth and simplifies the circuit complexity of the currently used serializer de-serializers (SerDes). Additionally, a feature of testability that covers different stuck-at faults was proposed to be implemented in the transmitter side of the proposed architecture. The complete proposed design was tested in TSMC 65 nm CMOS technology; it achieved a data rate of 10 Gbps running at the input clock frequency of 1.25 GHz. Moreover, a complete study of different components of a time mode transceiver architecture was performed during which different design implementation of TDC and phase locked loop (PLL) were thoroughly investigated. Last but not the least, different factors that are mainly imposed by the communication channel that affect the signal integrity were studied, and various methods both from a signal and a circuit point of view were investigated.