Virtual channel organization and arbitration for network on chip router architecure
thesisposted on 24.05.2021, 12:25 by Masoud Oveis Gharan
The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.